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advance information 02046-dsh-002-b mindspeed technologies? may 2004 advance information/mindspeed proprietary and confidential m02046 3.3/5v limiting amplifier for applications to 1.25 gbps advance information this document contains information on a product under development. the parametric information contains target parameters that are subject to change. applications ? 1.06 gbps fibre channel 1.25 gbps ethernet 1.25 gbps sdh/sonet the m02046 is a highly integrated high-gain limiting amplifier that can be used with the same board layout and foot- print as the mc2046-2. featuring pecl outputs, the m02046 is intended for use in applications to 1.25 gbps. full output swing is achieved even at minimu m input sensitivity. the m02046 can operate with a 3.3v or 5v supply. included in the m02046 is a programmable signal-level de tector, allowing the user to set thresholds at which the logic outputs are enabled. the signal detect function has typi cally 2 db (optical) of hysteresis which prevents chatter at low input levels. a squelch function, which turns off the outp ut when no signal is present, is provided by externally connecting the los status output to the jam input. the m02046 has a pecl status output and the m02046c has a cmos status output. both versions have a cmos los output. functional block diagram level detect limiting amplifier comparator dinn dinp pecln peclp offset cancel output buffer threshold setting circuit regulator v cc st set v cc3 biasing i ref jam v tt st los features pin compatible with the mc2046-2 operates with a 3.3 or 5v supply 2 mv input sensitivity at 1.25 gbps programmable input-s ignal level detect on-chip dc offset cancellation circuit cmos and pecl signal detect output variants output jam function low power (< 200 mw (m02046c) at 3.3v)
ii mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet ordering information part number package operating temperature M02046-XX pecl status output (cmos los output) in qsop16 package ?40 c to 85 c m02046c-xx cmos status output (cmo s los output) in qsop16 package ?40 c to 85 c m02046-pevm evaluation board with m02046 (pecl status output) ?40 c to 85 c m02046-cevm evaluation board with m02046c (cmos status output) ?40 c to 85 c note : xx represents the revision number. please contact your local sales office for correct digits. revision history revision level date asic revision description a advanced february 2004 -12 initial release b advanced may 2004 -12 remove references to rssi function
02046-dsh-002-b mindspeed technologies? iii advance information/mindspeed proprietary and confidential advance information table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 1.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 1.3.1 inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 1.3.2 dc offset compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.3.3 data outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.3.4 signal detect (st) and loss of signal (los) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.3.5 jam function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3.6 voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3.7 reference current generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.3.8 connecting vcc and vcc3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.3.9 choosing an input ac-coupling capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.3.10 setting the signal detect level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.3.11 peclp, pecln, and stpecl (m02046) termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.4 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.0 product specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.4 ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.5 package specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
iv mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet
02046-dsh-002-b mindspeed technologies? v advance information/mindspeed proprietary and confidential advance information list of figures figure 1-1. block diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 1-2. cml data inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 figure 1-3. pecl data outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 figure 1-4. pecl st output (m02046) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 figure 1-5. cmos st (m02046c) and los (m02046 and m02046c) output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 figure 1-6. stset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 1-7. jam input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 1-8. reference current generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 1-9. loss of signal characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 1-10. ac-coupled pecl termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 1-11. dc-coupled pecl termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 1-12. alternative pecl termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 2-1. data input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 2-2. typical applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 2-3. m02046 pinout - 16 pin qsop top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 2-4. package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
vi mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet
02046-dsh-002-b mindspeed technologies? vii advance information/mindspeed proprietary and confidential advance information list of tables table 1-1. rst resistor values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 1-2. pecl termination resistor values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 1-3. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 2-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 2-2. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 2-3. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 2-4. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
viii mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet
02046-dsh-002-b mindspeed technologies? 1 advance information/mindspeed proprietary and confidential advance information 1.0 functional description 1.1 overview the m02046 is a highly integrated high-gain limiting amplifier that can be used with the same board layout and footprint as the mc2046-2. featuring pecl outputs, the m02046 is intended for use in applications to 1.25 gbps. full output swing is achieved even at minimum input sensitivity. the m02046 can operate with a 3.3v or 5v supply. included in the m02046 is a programmable signal-level dete ctor, allowing the user to set thresholds at which the logic outputs are enabled. the signal detect function has ty pically 2 db (optical) of hysteresis which prevents chat - ter at low input levels. a squelch function, which turns off the output when no signal is present, is provided by exter - nally connecting the los status output to the jam input. the m02046 has a pecl status output and the m02046c has a cmos status output. both versions have a cmos los output. figure 1-1. block diagram example level detect limiting amplifier comparator dinn dinp pecln peclp offset cancel output buffer threshold setting circuit regulator v cc st set v cc3 biasing i ref jam v tt st los
2 mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet 1.2 features pin compatible with the mc2046-2 operates with a 3.3 or 5v supply 2 mv input sensitivity at 1.25 gbps programmable input-signal level detect on-chip dc offset cancellation circuit cmos and pecl signal detect output variants output jam function low power (< 200 mw (m02046c) at 3.3v) 1.3 general description the m02046 is a high-gain limiting amplifier for applications up to 1.25 gbps, and incorporates a limiting amplifier, an input signal level detection circuit and also a fully integrated dc-offset cancellation loop that does not require any external components. the m02046 features a pecl high-speed data outputs. the m02046 provi des the user with the flexibility to set the signal detect threshold and features either a pecl sta - tus output (m02046) or a cmos status output (m02046c). optional output buffer disable (squelch/jam) can be implemented using the jam input. 1.3.1 inputs the data inputs are internally connected to v tt via 50 ? resistors, and generally need to be ac coupled. referring to figure 1-2 , the nominal v tt voltage is 2.85v because of the internal resistor divider to v cc3 , which means this is the dc potential on the data inputs. see the applications information section for further details on choosing the ac- coupling capacitor. figure 1-2. cml data inputs v cc3 50 dinp v tt 50 dinn 8.3 k 1.3 k
functional description 02046-dsh-002-b mindspeed technologies? 3 advance information/mindspeed proprietary and confidential advance information 1.3.2 dc offset compensation the m02046 contain an internal dc autozero circuit that can remove the effect of dc offsets without using external components. this circuit is configured such that the feedback is effective only at frequencies well below the lowest frequency of interest. the low frequency cut off is typically 25 khz. 1.3.3 data outputs the m02046 features 100k/300k pecl compliant outputs as shown in figure 1-3 . the outputs may be terminated using any standard ac or dc-coupling pecl termination te chnique. ac-coupling is used in applications where the average dc content of the data is zero e.g. sonet. the advantage of this approach is lower power consumption, no susceptibility to dc drive and compatibility with no n-pecl interfaces. 1.3.4 signal detect (st) and loss of signal (los) the m02046 features input signal level detection over an extended range. using an external resistor, r st , between pin st set and v cc3 ( figure 1-6 ) the user can program the input signal threshold. the signal detect status is indicated on the both the signal detect (st) and los output pins. the status output is either pecl (m02046) or cmos (m02046c). the pecl version is shown in figure 1-4 while figure 1-5 shows the st output for the cmos version of the device (and the los output for both versions of the device). the st (los) signal is active (not asserted) when the sig nal is above the threshold value. the signal detection cir - cuitry has the equivalent of 4db (typical) electrical hysteresis. figure 1-3. pecl data outputs v cc v cc - 2v 50 50 d out p d out n
4 mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet r st establishes a threshold voltage at the st set pin as shown in figure 1-6 . internally, the input signal level is monitored by the level detector which creates a dc voltage proportional to the input signal peak to peak value. the voltage at st set is internally compared to the signal level from the level detector. when the level detect voltage is less than v (stset) , los is asserted and will stay asserted until the input signal level increases by a pre - defined amount of hysteresis. when the input level increases by more than this hysteresis above v (stset) , los is deasserted. see the applications information section for the selection of r st . note that st set can be left open if the loss of signal detector f unction is not required. in this case los would be low. figure 1-4. pecl st output (m02046) figure 1-5. cmos st (m02046c) and los (m02046 and m02046c) output st v cc v cc - 2v 50 either los o r st v cc 80 k
functional description 02046-dsh-002-b mindspeed technologies? 5 advance information/mindspeed proprietary and confidential advance information 1.3.5 jam function when asserted, the active high power down (jam) pin forces the outputs to a logic ?one? state. this ensures that no data is propagated through the system. the loss of signal detection circuit can be used to automatically force the data outputs to a high state when the input signal falls below the threshold. the function is normally used to allow data to propagate only when the signal is above the us er's bit-error-rate requirement. it therefore inhibits the data outputs toggling due to noise when there is no signal present (?squelch?). in order to implement this function, los should be connected to the jam pin shown in figure 1-7 , thus forcing the data outputs to a logic ?one? state when the signal falls below the threshold. 1.3.6 voltage regulation the m02046 contain an on-chip voltage regulator to allow both 5v and 3.3v operation. when used at 5v, the on- chip regulator is enabled and the digital inputs and outputs are compatible with ttl 5v logic levels. figure 1-6. stset input figure 1-7. jam input v cc3 st set r st v stset v cc jam v cc 55 k 100 k
6 mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet 1.3.7 reference current generation the m02046 contain an accurate on-chip bias circuit that requires an external 12.1 k ? 1% resistor, r ref , from pin i ref to ground to define an on-chip reference current. 1.3.8 connecting v cc and v cc3 for 5v operation, the v cc pin is connected to an appropriate 5v 7.5% supply. no potential should be applied to the v cc3 pin. the only connection to v cc3 should be r st as shown in figure 1-6 . when v cc = 5v all logic outputs and the data outputs are 5v compatible. for low power operation, v cc and v cc3 should be connected to an appropriate 3.3v 7.5% supply. in this case all i/os are 3.3v compatible. 1.3.9 choosing an inpu t ac-coupling capacitor when ac-coupling the input the coupling capacitor should be of sufficient value to pass the lowest frequencies of interest, bearing in mind the number of consecutive identic al bits, and the input resistance of the part. for sonet data, a good rule of thumb is to chose a coupling capacitor that has a cut-off frequency less than 1/(10,000) of the input data rate. for example, for 1.25 gbps data, the coupling capacitor should be chosen as: f cutoff (1.25x10 9 / 10x10 3 ) = 125 khz the -3 db cutoff frequency of the low pass filter at the 50 ? input is found as: f 3db = 1/ (2 * * 50 ? * c ac ) so solving for c where f 3db = f cutoff c ac = 1/ (2 * * 50 ? * f cutoff ) eq.1 and in this case the minimum capacitor is 25 nf. for ethernet or fibre channel, there are less consecutive bits in the data, and the recommended cut-off frequency is 1/(1,000) of the input data rate. this results in a minimum capacitor of 2.5 nf for 1.25 gbps ethernet. figure 1-8. reference current generation i ref + - 12.1 k r ref v cc
functional description 02046-dsh-002-b mindspeed technologies? 7 advance information/mindspeed proprietary and confidential advance information multirate applications down to 155 mbps in this case, the input coupling capacitor needs to be large enough to pass 15 khz (155x10 6 /10,000) which results in a capacitor value of 0.2 f. however, because this low pass frequency is close to the 25 khz low pass frequency of the internal dc servo loop, it is preferable to use a larger input coupling capacitor such as 1 f which provides an input cutoff frequency of 3.1 khz. this separates the two poles sufficiently to allow them to be considered inde - pendent. this capacitor should also have a 20 nf capacitor in parallel to pass the higher frequency data (in the multirate application) without distortion. in all cases, a high quality coupling capacitor should be used as to pass the high frequency content of the input data stream. 1.3.10 setting the signal detect level using figure 1-9 , the value for r st is chosen to set the los threshold at the desired value. the resulting hystere - sis is also shown in figure 1-9 . from figure 1-9 , it is apparent that small variations in r los cause significant variation in the los threshold level, particularly for low input sign al levels. this is because of the logarith mic relationship between the internal level detect voltage and the input signal level. it is recommended that a 1% resistor be used for r st and that allowance is provided for los variation, particularly when the lo s threshold is near the sensitivity limit of the m02046. example r st resistor values are given in table 1-1 . table 1-1. r st resistor values vin (mv pp) differential r st (k ? ) 6.9 11.0 9.9 10.7 13.0 10.5 18.8 10.2 23.4 10.0
8 mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet 1.3.11 peclp, pecln, and st pecl (m02046) termination the data and st (in the pecl version of the part) outputs of the m02046 are pecl compatible. for the high speed peclp and pecln outputs any standard ac or dc-coupling termination technique can be used. figure 1-10 and figure 1-11 illustrate typical ac and dc terminations. ac-coupling is used in applications where the average dc content of the data is zero e.g. sonet. the advantage of this approach is lower power c onsumption, no susceptibilit y to dc drift and compat ibility with non-pecl inter - faces. figure 1-10 shows the circuit configuration and table 1-2 lists the resistor values. if using transmission lines other than 50 ? , the shunt terminating resistance z t should equal twice the impedance of the transmission line (z o ). dc-coupling can be used when driving pecl interfaces an d has the advantage of a reduced component count. a thevenin termination is used at the receive end to give a 50 ? load and the correct dc bias. figure 1-11 shows the circuit configuration and table 1-2 the resistor values. alternatively, if available, terminating to v cc - 2v as shown in figure 1-12 has the advantage that the resistance value is the same for 3.3 v and 5 v operation and it also has performance advantages at high data rates. in the m02046, st is a pecl output. it is recommended that it be dc terminated in a pecl load, preferably as shown in figure 1-12 , but the decoupling capacitor on the load is not required as this is a dc output. figure 1-9. loss of signal characteristic table 1-2. pecl termination resistor values supply output impedance r pull-down z t r ta / r tb r t / r b 5 v 50 ? 270 ? 100 ? 2.7 k ? / 7.8 k ? 82 ? / 130 ? 3.3 v 50 ? 150 ? 100 ? 2.7 k ? / 4.3 k ? 130 ? / 82 ? threshold level (mv pp ) 0 5 10 15 20 25 30 35 40 10.0 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11.0 conditions: 1.25 gbps, 2 31 - 1 vcc = 3.3v, temp = 25c optical hysteresis assert de-assert r st (k ? ) = 10*log 10 (de-assert/assert)
functional description 02046-dsh-002-b mindspeed technologies? 9 advance information/mindspeed proprietary and confidential advance information figure 1-10. ac-coupled pecl termination figure 1-11. dc-coupled pecl termination v cc m02046 peclp z o z t r pu ll- d own pecl 0.1f v cc r ta r tb 0.1f r tb r ta pecln z o v cc m02046 z o pecl v cc r t r b r b r t z o 10 nf peclp pecln
10 mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet figure 1-12. alternative pecl termination v cc z o pecl z o 10 nf v cc v cc - 2v 50 50 m02046 peclp pecln
functional description 02046-dsh-002-b mindspeed technologies? 11 advance information/mindspeed proprietary and confidential advance information 1.4 pin definitions table 1-3. pin descriptions qsop pin# name function 1st set loss of signal threshold setting input. conn ect a 1% resistor between this pin and v cc3 to set loss of signal threshold. 2v cc3 power supply input for 3.3v applications or the output of the internally regulated 3.3v voltage when v cc = 5v. connect directly to supply for 3.3v applications (interna l regulator not in use). do not connect to power supply if v cc = 5v. 3 gnd ground. 4 dinp non-inverting data input. internally terminated with 50 ? to v tt . 5 dinn inverting data input. internally terminated with 50 ? to v tt . 6 nc no connect. leave floating. 7v cc3 power supply input for 3.3v applications or the output of the internally regulated 3.3v voltage when v cc = 5v. connect directly to supply for 3.3v applications (interna l regulator not in use). do not connect to power supply if v cc = 5v. 8 jam output disable. when high, data outputs are disabled (with non-inverting out put held high and inverting output held low). connect to los output to di sable outputs with loss of signal. out puts are enabled when jam is low or floating. internal 150k ? resistor to ground. 9 los loss of signal output. goes high when i nput signal falls below threshold set by st set . this output is an open collector ttl with internal 80k ? pull-up resistor to v cc . leave floating if not used. 10 st signal detect output. goes high when input si gnal amplitude is above threshold set by st set . in m02046c, this output is an open collect or ttl with internal 80k ? pull-up resistor to v cc ; in m02046, this output is pecl. leave floating if not used. 11 gnd ground. 12 pecln inverting data output (pecl). 13 peclp non-inverting data output (pecl). 14 v cc power supply. connect to either +5v or +3.3v. 15 nc no connect. leave floating. 16 i ref internal reference current. must be connected to ground through a 12.1k ? 1% resistor.
12 mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet
02046-dsh-002-b mindspeed technologies? 13 advance information/mindspeed proprietary and confidential advance information 2.0 product specification 2.1 absolute maximum ratings these are the absolute maximum ratings at or beyond which the ic can be expected to fail or be damaged. reli - able operation at these extremes for any length of time is not implied. note: the package bottom must be adequately grounded to ensure correct thermal and electrical performance, and it is recommended that vias are inserted through to a lower ground plane. table 2-1. absolute maximum ratings symbol parameter rating units v cc power supply voltage (v cc -gnd) -0.5 to +6v v t stg storage temperature -65 to +150 c peclp, pecln, st pecl pecl output pins voltage v cc -2 to v cc + 0.4 v i(peclp), i(pecln), i(st pecl ) pecl output pins maximum continuous current (delivered to load) 30 ma |dinp - dinn| data input pins differential voltage 0.80 v dinp, dinn data input pins voltage meeting |dinp - dinn| requirement gnd to v cc3 + 0.4 v st set signal detect threshold set ting pin voltage gnd to v cc + 0.4 v jam output enable pin voltage gnd to v cc + 0.4 v st cmos , los cmos status output pins voltage gnd to v cc + 0.4 v i ref current into reference input +0 to -120 a i(los), i(st cmos ) current into cmos status output pins +1500 to -100 a
14 mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet 2.2 recommended operating conditions 2.3 dc characteristics v cc = +3.3v 7.5% or +5v 7.5%, t a = -40c to +85c, unless otherwise noted. typical specifications are for v cc = 3.3v, t a = 25c, unless otherwise noted. notes: 1. m02046c 2. m02046 table 2-2. recommended operating conditions parameter rating units power supply: (v cc -gnd) (apply no potential to v cc3 ) or (v cc3 -gnd) (connect v cc to same potential as v cc3 ) +5v 7.5% or +3.3v 7.5% v junction temperature -40 to +110 c operating ambient -40 to +85 c table 2-3. dc characteristics symbol parameter conditions min typ max units i cc supply current includes pecl load 52 tbd ma v outlpecl pecl output low voltage (peclp, pecln) single ended; 50 ? load to v cc - 2v v cc -1.81 v cc -1.71 v cc -1.62 v v outhpecl pecl output high voltage (peclp, pecln) single ended; 50 ? load to v cc - 2v v cc -1.025 v cc -0.952 v cc -0.88 v differential input resistance measu red between dinp and dinn 85 100 115 ? cmos st (1 ) , los (1, 2 ) output high voltage external 4.7-10k ? pull up to v cc 2.4 v cc v cmos st (1 ) , los (1, 2 ) output low voltage external 4.7-10k ? pull up to v cc 00.4v pecl st output high voltage (2 ) st terminated 50 ? to v cc - 2v v cc -1.025 v cc -0.952 v cc -0.88 v pecl st output low voltage (2 ) st terminated 50 ? to v cc - 2v v cc -1.81 v cc -1.71 v cc -1.62 v jam input high voltage 2.7 5.5 v jam input low voltage 0.8 v
product specification 02046-dsh-002-b mindspeed technologies? 15 advance information/mindspeed proprietary and confidential advance information 2.4 ac characteristics v cc = +3.3v 7.5% or +5v 7.5%, t a = -40c to +85c, input bit rate = 2.5 gbps 2 23 -1 prbs unless otherwise noted. typical specifications are for v cc = 3.3v, t a = 25c, unless otherwise noted. table 2-4. ac characteristics symbol parameter conditions min typ max units v in(min)) differential input sensitivity 1.25 gbps, ber < 10 -12 4mv v i(max) input overload ber < 10 -12 , differential input 1.25 gbps 1200 mv ber < 10 -12 , single-ended input, 1.25 gbps 600 mv v n rms input referred noise 185 v rms v sd signal detect programmable range differential inputs 4 100 mv hys signal detect hysteresis (electri cal); signal detect level set to 20 mv pp 246db bw lf small-signal ?3db low frequency cutoff excluding ac coupling capacitors 25 khz dj deterministic jitter k28.5 pattern at 1.25 gbps 25 ps rj random jitter 10 mv pp input 3 ps rms t r / t f data output rise and fall times 20% to 80%; outputs terminated into 50 ?; 10 mv pp input 185 300 ps t los_on time from los state until los output is asserted los assert time after 1 vpp input signal is turned off; signal detect level set to 10 mv 100 s t los_off time from non-los state until los is deasserted los deassert time after input crosses signal detect level; signal detect set to 10 mv with applied input signal of 20 mv pp 100 s figure 2-1. data input requirements dinp dinn 2 - 600 mv 4 - 1200 mv differential input single-ended input dinp or dinn 4 - 600 mv unused input
16 mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet note: for single-ended input connections. when connecting to the used input with ac-coupling, the unused input should be ac-coupled through 50 ? to the supply voltage of the tia; when connecting to the used input with dc-coupling, the unused input should be dc-coupled through 50 ? to a voltage equal to the common mode level of the used input. figure 2-2. typical a pplications circuit note: applies for v cc = 5v or 3.3v. ac-coupled inputs shown. optional limiting amplifier comparator dinn dinp pecln peclp offset cancel output buffer threshold setting circuit regulator v cc st set v cc3 biasing i ref jam los ac-coupled to tia r st 12.1 k v tt level detect st
product specification 02046-dsh-002-b mindspeed technologies? 17 advance information/mindspeed proprietary and confidential advance information 2.5 package specification figure 2-3. m02046 pinout - 16 pin qsop top view figure 2-4. package information m02046-12 date code 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd jam dinp set st v cc3 dinn nc v cc3 nc gnd st los pecln peclp v cc i ref ee1 bottom view seating plane stand-off a1 stand-off symbol tols/n qsop16 a max. 1.60 a1 .05 0.1 a2 .05 1.40 d .05 4.95 e .10 6.00 e1 .05 3.90 l .15 0.60 ccc max. 0.080 ddd max. 0.10 e basic 0.635 b .025 0.224 c .02 0.22 r .05 0.25 r1 min. 0.20
18 mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet
advance information 02046-dsh-002-b mindspeed technologies? 19 advance information/mindspeed proprietary and confidential ? 2004, mindspeed technologies tm , inc. all rights reserved. information in this document is provided in connection with mindspeed technologies tm ("mindspeed tm ") products. these materials are provided by mindspeed as a service to its customers and may be used for informational pur- poses only. except as provided in mindspeed?s terms a nd conditions of sale for such products or in any sepa- rate agreement related to this document, mindspeed a ssumes no liability whatsoever . mindspeed assumes no responsibility for errors or omissions in these materials. mindspeed may make changes to specifications and prod- uct descriptions at any time, without notice. mindspeed makes no commitment to update the information and shall have no responsibility wh atsoever for conflicts or incomp atibilities arising from future changes to its specifications and product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. these materials are provided "as is" without warranty of any kind, either express or implied, relating to sale and/or use of mindspeed products including liability or war- ranties relating to fitness for a particul ar purpose, consequential or incidental damages, merchantability, or infringement of any patent, copyright or other intellec- tual property right. mindspeed further do es not warrant the accuracy or complete- ness of the information, text, graphics or other items contained within these materials. mindspeed shall not be liable for an y special, indirect, incidental, or conse- quential damages, including without limitati on, lost revenues or lost profits, which may result from the use of these materials. mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. mindspeed cus- tomers using or selling mindspeed products for use in such applications do so at thei r own risk and agree to fully indemnify mindspeed for any damages resulting from such improper use or sale.
20 mindspeed technologies? 02046-dsh-002-b advance information/mindspeed proprietary and confidential advance information m02046 data sheet www.mindspeed.com general information: u.s. and canada: (800) 854-8099 international: (949) 483-6996 headquarters - newport beach 4000 macarthur blvd., east tower newport beach, ca. 92660

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